Cadence Design Systems
- 2655 Seely Avenue Bldg 5
- San Jose, CA
1 review
Experienced Employee: I worked as an analog layout engineer for 4 years at Cadence Design Systems, Bangalore. In my course of learning and experimentation, I worked on multiple DDR, SERDES and PHY projects. I was also encouraged to try my skills in automation using Cadence Skill, Perl, PVS and SVRF languages. Various technologies worked on include TSMC(28nm,16nm,12nm and 7nm), Samsung(10nm, 8nm and 7nm) and UMC(28nm). The environment is educative(I would get to learn a new thing everyday), friendly(I could approach absolutely anyone with my questions), encouraging(I always got a chance to explore my ideas and try it my way) and most of all passionate(Every person here is extremely passionate about chip designing and deep discussions are always encouraged). I found several great mentors and multiple people that I can look up to. It has overall been a great journey.
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Technology Industry
— Employees